Data transmission at extremely high rates is conventionally carried out by means of serial data streams arranged into packets or frames. Fiber Optic line transmission is becoming increasingly popular at rates of 10 G bits/sec and above.
Conversion and realignment of Sonet OC-192 based standard data streams at 10 Gbit/sec from optical to electrical and then back to optical is an essential part of the process of realizing any high-speed switch fabric in the optical networking discipline. This is because the optical data signals passed from one location to another suffer attenuation in the transmission lines and must be refreshed at intervals in the transmission. This is done by means of receive-transmit modules referred to as repeaters or alternately serial links. Conventional repeaters include a receiver, a data processor, a clock recovery circuit and a transmitter. The receiver includes an optical-to-electrical converter and first stage serial-to-parallel converter/demultiplexer. The data processor is typically an ASIC chip. This ASIC chip performs a variety of tasks such as error detection and correction, forward error correction re-coding, second stage serial-to-parallel conversion and parallel-to-serial conversion. The clock recovery circuit typically includes bipolar Gallium-Arsenide modules. The transmitter includes an electrical-to-optical converter/multiplexer and an optical fiber line driver.
In conventional systems, discrete clock recovery modules in bipolar Gallium-Arsenide technology are used for repeater modules of high performance requirements. ASIC modules perform only the lower performance functions. The required use of bipolar Gallium-Arsenide technology with ASIC technology in the same repeater represents a technology mismatch and has hindered the growth of transmission bandwidth in optical networks.
FIG. 1 illustrates a common prior art construction of a repeater module. The system illustrated is representative of an OC-48 standard 2.4 Gigabit/second (Gb/s) technology. The repeater includes optical-to-electrical demultiplexer 101, ASIC processor 102, clock/data recovery modules (CDR) 103, 104, 105, and 106, and electrical-to-optical multiplexer 107.
Input data stream 100 and output data stream 109 are both 2.4 Gb/s. Both optical-to-electrical converter 101 and electrical-to-optical converter 108 employ special mixed-signal technology with significant portions of the circuits performing at the 2.4 GHz rate. In optical-to-electrical converter 101, the data is typically sampled at the 2.4 GHz rate and a phase adjustment is made on the sampling clock for optimal data recovery. This requires phase lock loop techniques beyond the scope of this description. An additional result of this synchronization and data recovery is that an output clock 110 is generated for operation of the ASIC processor 102. Serial link modules using the building blocks of FIG. 1 vary markedly by application. If the layout of the serial link module as a whole requires physical routing of the clock over significant interconnect lengths, then clock recovery may be necessary within the functional block receiving that clock.
Special timing requirements in the conventional 2.4 Gb/s rate systems have made plural clock/data recovery elements 103 to 107 necessary. These elements use of discrete Gallium-Arsenide bipolar transistor circuits that dissipate a significant amount of power, on the order of several watts. In conventional designs these specific circuits were not suited to integration with the ASIC processor 102, which is typically constructed of complementary metal oxide semiconductor (CMOS). Thus the power dissipation of such a conventional multi-technology electrical-optical repeater system as well as the technology mismatch limits their large-scale use to increase data bandwidth.
In the conventional optical-to-electrical repeater systems, each of four 622 Mb/s data streams have a companion clock signal. FIG. 1 illustrates two such pairs data 110 and clock 111, and data 120 and clock 121. Clock recovery is carried out in a bit-stream by bit-stream basis, requiring multiple high power dissipation clock recovery circuits.
Optical-to-electrical demultiplexer 101 receives a 2.4 Gb/s rate data stream generated by amplitude modulation of the coherent light carrier in the 1 micron wavelength range. The data at the 2.4 GHz rate is super-imposed on the laser light stimulus to a laser diode. Thus the data 100 could have been generated at the input end of the system or could have been re-generated by an up-stream repeater. In long fiber optic lines repeaters are required at intervals of several miles or tens of miles.
Optical-to-electrical demultiplexer 101 receives a 2.4 Gb/s data stream with native synchronization to a 2.4 GHz modulation source. The 1:4 demultiplexing operation of block 101 noted in FIG. 1 is a by-product of the optical-to-electrical conversion process. This demultiplexing operation uses techniques employed in asynchronous mode transfer ATM systems. Table 1 compares the input/output data rates and internal processing data rate for each of the Sonet standards of interest here.
TABLE 1SerialParallelSonetData RateParallel Data RateStandardInput/OutputInternal ProcessingOC-48 2.4 GHz150 MHzOC-192 10 GHz622 MHzOC-768 40 GHz622 MHz
The conventional Sonet OC-48 ASIC Processor 102 includes the following functional blocks: asynchronous serial data input interface; data frame format interpreter; control signal generator for processor configuration; data acquisition and temporary storage; serial-to-parallel data convertor from 4-bit data to 32 bit data; data processor for error detection/correction unit, data recoding and reformating; output pipeline first-in-first-out (FIFO) memory; and transmit module including parallel-to-serial converter from 32-bit data to 4-bit data and four-bit stream serial data output interface.